SoC GDS SoC GDS project is a System-on-Chip Graphic Display Streamer.
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EDA Electronic Design Automation Graphic Display Streamer SoC GDS

SoC GDS Description

SoC GDS project is a System-on-Chip Graphic Display Streamer. SoC GDS project is a System-on-Chip Graphic Display Streamer.Here are some key features of "SoC GDS":· Load multiple GDSII libraries with no size limits,· Load gzipped GDSII libraries,· Use full ruler and gridding functions,· Display layout with unrestricted zoom functions,· Configure layer display attributes,· Use restricted hierarchy navigation,· Load Cadence techfiles.SoC GDS View is the entry-level option providing optimized GDSII display capabilities including color and pattern configuration file compatibility with Cadence for drop-in replacement or complementing in design flows.SoC GDS Multi Frame extends the speed and power of SoC GDS View with advanced hierarchical navigation, input format support complemented with OpenAccess and LEF, as well as (VC)LEF generation. Verification of layouts is accelerated through hierarchical graphic cell comparison and hierarchical display of nets annotated by SoC GDS Contrast. SoC GDS MultiFrame slashes load-times and delivers unmatched verification and validation technology.SoC GDS Integrator enables socket creation and verification for system-level integration of ViCs (Virtual Components) as defined by VSIA (Virtual Socket Interface Alliance). Delivery of layouts is accelerated through LVS socket creation improvements, hierarchical geometrical cell comparison and a powerful interpreted scripting language for repetitive processing.The new Virtual Cut feature allows to extract just a part of a layout for verification while totally preserving data confidentiality of the rest of the SoC. SoC GDS Integrator provides full OpenAccess DataBases support (reading and writing).SoC GDS Contrast couples SoC GDS Integrator with our patent pending eMicroscope technology to superpose simulation results from extracted netlists directly onto the layout. SoC GDS Contrast shortens your development cycles and reduces post-fabrication failures by enabling Virtual Test & Diagnostic before manufacturing test chips. Delaying electron microscopy experiments until test chips are actually manufactured is costing you money right now. SoC GDS contrast is going to shorten your development cycles and reduce post-fab failures.What's New in This Release:· The layer configuration window has been enhanced to show the layer and data type numbers in the loaded map table, as well as unmapped layers.· An abstract versus layout comparator has been implemented that allows automatically comparing all macros in a LEF with the corresponding GDSII cell, based on comparison of obstruction and port geometries.· SoC GDS is now also available under Red Hat Enterprise Linux 4 in 64-bit mode.

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