Environment for Embedded Software VerificationTranslate UML sequences with this instrument | |
Download |
Environment for Embedded Software Verification Ranking & Summary
Advertisement
- License:
- GPL
- Publisher Name:
- Marcelo M. Custodio
- Operating Systems:
- Windows All
- File Size:
- 57 KB
Environment for Embedded Software Verification Tags
Environment for Embedded Software Verification Description
Environment for Embedded Software Verification is built as an environment that is able to translate UML Sequence Diagrams to Petri Nets and verify system properties with SMV. The tool receives as input sequence diagrams of UML and provides the Petri net in three different formats: · APNN, · PNML, · SMV.
Environment for Embedded Software Verification Related Software